OR Gate

The PomeLabs OR Gate Module (PML-OG-01) is the kit's most permissive logic gate — output HIGH the moment either input goes HIGH, LOW only when both go silent simultaneously. Unlike the configurable IC behind the AND, NOT, and XOR modules, this one uses a dedicated, fixed-function OR gate: no configuration pins, no ambiguity, just $3.6\,\mathrm{ns}$ of clean positive-OR logic from $1.65\,\mathrm{V}$ to $5.5\,\mathrm{V}$ .

Revision: v1.0 | Part Number: PML-OG-01 | Series: PomeLabs Core Kit

Schematic

Or Gate Schematic

Digital Twin

In the PomeLabs App, the PML-OG-01 is mirrored as a digital twin in both the Playground and inside any Connect Activity. On connection the module reports its unique ID, firmware version, and type, and the App places it in your circuit by reading the live netlist — so you always see which module it is and how it is wired. Its combinational logic runs entirely on the physical gate IC; the current release exposes no app-side controls or streamed values for this module.

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Datasheet

1. Overview

The PML-OG-01 implements a 2-input OR gate using the SN74LVC1G32DCKR (U1) — a dedicated, fixed-function single 2-input positive-OR gate from Texas Instruments. Unlike the configurable SN74LVC1G99 used in the AND and NOT Gate Modules, this IC is purpose-built: $Y = A + B$ with no configuration pins required.

This architectural choice is intentional and instructive. The OR Gate Module sits alongside the configurable gate modules precisely to show students the two design philosophies in digital IC design — a fixed-function part optimized for propagation delay ( $3.6\,\mathrm{ns}$ max at $3.3\,\mathrm{V}$ versus $7.5\,\mathrm{ns}$ for the configurable gate's A/B inputs) versus a programmable part optimized for flexibility. Both approaches have their place in real hardware design.

Output Y drives both S+_UR and S+_LR simultaneously, allowing two downstream modules to observe the same gate output in parallel.

2. BOM Components

Ref.	Type	Value / Part	Role on this module
U1	Single 2-input OR gate	SN74LVC1G32DCKR (TI)	Dedicated fixed-function positive-OR gate. $Y = A + B$ . No configuration pins. $1.65$ – $5.5\,\mathrm{V}$ supply, inputs accept up to $5.5\,\mathrm{V}$ . $\pm 24\,\mathrm{mA}$ output drive at $V_{CC}$ = $3\,\mathrm{V}$ , $t_{pd}$ = $3.6\,\mathrm{ns}$ max at $3.3\,\mathrm{V}$ . SC70-5 (DCK) package, $2.00 \times 2.10\,\mathrm{mm}$ .
R1–R4	Resistor	$4.7\,\mathrm{k\Omega}$	Pull-up resistors on UART TX/RX lines to 3V3. Hold the lines at a defined HIGH idle state when no node is connected.
p1–p4	Connector	Node headers	Four node connectors exposing +5V, GND, S+, S−, RX/TX, TX/RX to downstream modules.

3. Electrical Specifications

All values at $25\,\mathrm{{}^\circ C}$ unless otherwise noted. Gate specifications from TI SCES219V (SN74LVC1G32, Rev. V, Aug 2015).

3.1 U1 — SN74LVC1G32DCKR

The SN74LVC1G32 is a single 2-input positive-OR gate designed for $1.65\,\mathrm{V}$ to $5.5\,\mathrm{V}$ $V_{CC}$ operation. The CMOS device has high output drive while maintaining low static power dissipation across its full supply range. The device is fully specified for partial-power-down applications using the $I_{off}$ feature, which disables the outputs to prevent damaging current backflow when $V_{CC}$ = $0\,\mathrm{V}$ .

3.1.1 Absolute Maximum Ratings

Exceeding these values may permanently damage the device. Stress ratings only.

Parameter	Max Value	Unit
Supply voltage ( $V_{CC}$ )	$-0.5$ to $6.5$	V
Input voltage ( $V_I$ )	$-0.5$ to $6.5$	V
Output voltage — high-impedance or power-off state ( $V_O$ )	$-0.5$ to $6.5$	V
Output voltage — high or low state ( $V_O$ )	$-0.5$ to $V_{CC} + 0.5$	V
Input clamp current ( $I_{IK}$ ), $V_I < 0$	$-50$	mA
Output clamp current ( $I_{OK}$ ), $V_O < 0$	$-50$	mA
Continuous output current ( $I_O$ )	$\pm 50$	mA
Continuous current through $V_{CC}$ or GND	$\pm 100$	mA
ESD — Human Body Model (HBM)	$\pm 2000$	V
ESD — Charged Device Model (CDM)	$\pm 1000$	V
Junction temperature ( $T_J$ )	$-65$ to $+150$	°C
Storage temperature ( $T_{stg}$ )	$-65$ to $+150$	°C

3.1.2 Recommended Operating Conditions

Parameter	Min	Max	Unit / Notes
Supply voltage ( $V_{CC}$ ) — operating	$1.65$	$5.5$	V
Supply voltage ( $V_{CC}$ ) — data retention only	$1.5$	—	V
High-level input voltage ( $V_{IH}$ ) @ $V_{CC}$ = $3\,\mathrm{V}$ to $3.6\,\mathrm{V}$	$2.0$	—	V
Low-level input voltage ( $V_{IL}$ ) @ $V_{CC}$ = $3\,\mathrm{V}$ to $3.6\,\mathrm{V}$	—	$0.8$	V
Input voltage ( $V_I$ )	$0$	$5.5$	V — inputs accept up to $5.5\,\mathrm{V}$ regardless of $V_{CC}$
Output voltage ( $V_O$ )	$0$	$V_{CC}$	V
High-level output current ( $I_{OH}$ ) @ $V_{CC}$ = $3\,\mathrm{V}$	—	$-24$	mA — sourcing
Low-level output current ( $I_{OL}$ ) @ $V_{CC}$ = $3\,\mathrm{V}$	—	$24$	mA — sinking
High-level output current ( $I_{OH}$ ) @ $V_{CC}$ = $4.5\,\mathrm{V}$	—	$-32$	mA — sourcing
Low-level output current ( $I_{OL}$ ) @ $V_{CC}$ = $4.5\,\mathrm{V}$	—	$32$	mA — sinking
Input transition rise/fall rate ( $\Delta t / \Delta v$ ) @ $V_{CC}$ = $3.3\,\mathrm{V}$	—	$10$	ns/V
Operating temperature ( $T_A$ ) — DCK package	$-40$	$125$	°C

3.1.3 Electrical Characteristics

Parameter	Typical	Max	Condition
High-level output voltage ( $V_{OH}$ )	—	$V_{CC} - 0.1$	V — $I_{OH}$ = $-100\,\mathrm{\mu A}$ , $V_{CC}$ = $1.65\,\mathrm{V}$ to $5.5\,\mathrm{V}$
High-level output voltage ( $V_{OH}$ )	—	$2.3\,\mathrm{V}$	$I_{OH}$ = $-24\,\mathrm{mA}$ , $V_{CC}$ = $3\,\mathrm{V}$
Low-level output voltage ( $V_{OL}$ )	—	$0.55\,\mathrm{V}$	$I_{OL}$ = $24\,\mathrm{mA}$ , $V_{CC}$ = $3\,\mathrm{V}$
Input leakage current ( $I_I$ )	—	$\pm 5\,\mathrm{\mu A}$	$V_I$ = $5.5\,\mathrm{V}$ or GND
Power-off leakage ( $I_{off}$ )	—	$\pm 10\,\mathrm{\mu A}$	$V_I$ or $V_O$ = $5.5\,\mathrm{V}$ , $V_{CC}$ = $0\,\mathrm{V}$
Quiescent supply current ( $I_{CC}$ )	—	$10\,\mathrm{\mu A}$	$V_I$ = $V_{CC}$ or GND, $I_O$ = $0$
Supply current change ( $\Delta I_{CC}$ )	—	$500\,\mathrm{\mu A}$	one input at $V_{CC} - 0.6\,\mathrm{V}$
Input capacitance ( $C_i$ )	$4\,\mathrm{pF}$	—	$V_{CC}$ = $3.3\,\mathrm{V}$
Power dissipation capacitance ( $C_{pd}$ )	$21\,\mathrm{pF}$	—	$V_{CC}$ = $3.3\,\mathrm{V}$ , $f$ = $10\,\mathrm{MHz}$

4. Function Table

$Y = A + B$ in positive logic. Output HIGH whenever at least one input is HIGH.

A (S+_UL)	B (S+_LL)	Y Output (S+_UR / S+_LR)
L	L	L — both inputs LOW, output LOW
L	H	H — at least one input HIGH, output HIGH
H	L	H — at least one input HIGH, output HIGH
H	H	H — both inputs HIGH, output HIGH

(Equivalent to TI's compact table form: any H on an input forces Y HIGH; only L–L gives L.)

5. Pin Descriptions

All signal pins are referenced to GND.

Pin / Net Name	Direction	Description
S+_UL	Input	Logic input A to U1. Upper-Left signal. Output Y goes HIGH when this input is HIGH, regardless of B.
S+_LL	Input	Logic input B to U1. Lower-Left signal. Output Y goes HIGH when this input is HIGH, regardless of A.
S+_UR / S+_LR	Output	OR gate output Y. HIGH when either or both inputs are HIGH; LOW only when both are LOW. Drives both output channels simultaneously.
5V-Module	Power In	$5\,\mathrm{V}$ supply. Powers $V_{CC}$ of U1.
GND	Ground	Common ground for all ICs and connectors.

6. Connection Guide & Common Errors

Correct power-up sequence:

Connect GND first, shared across all modules on the common bus.
Connect 5V-Module to a regulated $5\,\mathrm{V}$ source. This powers $V_{CC}$ of U1.
Connect the 3V3 rail for the UART pull-up resistors R1–R4.
Apply logic signals to S+_UL (A) and S+_LL (B). The output appears immediately on S+_UR / S+_LR with $t_{pd} \leq 3.6\,\mathrm{ns}$ at $3.3\,\mathrm{V}$ .

Logic-level reference at $V_{CC}$ = $3.3\,\mathrm{V}$ : an input must rise above $V_{IH}$ = $2.0\,\mathrm{V}$ to register as HIGH and fall below $V_{IL}$ = $0.8\,\mathrm{V}$ to register as LOW. The SN74LVC1G32 uses standard CMOS inputs (no Schmitt-trigger hysteresis), so signals between $0.8\,\mathrm{V}$ and $2.0\,\mathrm{V}$ are in the indeterminate region and may produce unexpected output behaviour. For slow or noisy signals, consider routing through the NOT Gate Module first (which has a Schmitt-trigger input).

Common wiring errors and consequences:

Mistake	Symptom	Correction
Input A or B left floating	Floating CMOS input drifts; output Y may toggle randomly or hold indeterminate state	Always drive both inputs from a defined logic source. If only one input is needed, tie the unused input to GND — for an OR gate, GND on the unused input passes the active input through unchanged (since L OR x = x).
$V_{CC}$ to U1 exceeds $5.5\,\mathrm{V}$	U1 permanently damaged (absolute max $6.5\,\mathrm{V}$ )	Keep 5V-Module rail $\leq 5.5\,\mathrm{V}$ .
Input signal exceeds $5.5\,\mathrm{V}$	Input clamp current flows; permanent damage if $I_{IK}$ exceeds $50\,\mathrm{mA}$	Inputs are $5.5\,\mathrm{V}$ tolerant — never exceed it. Add a series resistor if your source can swing higher.
Output Y driving load $> 50\,\mathrm{mA}$	Continuous output current absolute max exceeded — U1 may overheat or fail	Keep total $I_O$ on S+_UR + S+_LR within $\pm 50\,\mathrm{mA}$ absolute max. For sustained operation, design for $\pm 24\,\mathrm{mA}$ at $3\,\mathrm{V}$ or $\pm 32\,\mathrm{mA}$ at $4.5\,\mathrm{V}$ .
Very slow input edges (slower than $10\,\mathrm{ns/V}$ at $3.3\,\mathrm{V}$ )	Operation outside the guaranteed input transition rate; the output may glitch through the indeterminate input region	Buffer slow analog-like signals with a Schmitt-trigger stage (such as the NOT Gate Module) before feeding them to S+_UL or S+_LL.
Driving inputs while 5V-Module is OFF	$I_{off}$ circuitry isolates U1 and prevents back-drive damage — designed-in safe condition, not a fault	No action needed; partial-power-down via $I_{off}$ is supported by the device.
GND not shared with downstream modules	Ground offset corrupts $V_{IH}$ / $V_{IL}$ thresholds across modules; output may appear correct on a scope but downstream module sees wrong level	Ensure a single common GND bus across the Backend MCU, the OR Gate Module, and every downstream module.

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