OpAmp

The PomeLabs Op-Amp Module (PML-OA-01) is a snap-together analog building block that brings the full power of a precision operational amplifier into the PomeLabs ecosystem — no breadboard, no wiring errors, just connect and experiment.

Revision: v1.0 | Part Number: PML-OA-01 | Series: PomeLabs Core Kit

Schematic

OpAmp Schematic

Digital Twin

In the PomeLabs App, the PML-OA-01 module is mirrored as a digital twin in both the Playground (free-form circuit sandbox) and inside any Connect Activity (guided lab). On connection the module reports its unique ID, firmware version, and type, and the App places it in your circuit by reading the live netlist — so you always see which module it is and how it is wired. Its analog behaviour runs entirely on the physical hardware; the current release exposes no app-side controls or streamed values for this module.

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Datasheet

1. Overview

The PML-OA-01 centers on a TL081HIDR JFET-input operational amplifier (U1), chosen for its $5.25\,\mathrm{MHz}$ gain-bandwidth product, $20\,\mathrm{V/\mu s}$ slew rate, and sub- $2\,\mathrm{mV}$ input offset — performance characteristics that make it suitable for audio, instrumentation, and control circuit experiments at the educational level. A key design decision is the onboard LM2776DBVR switched-capacitor voltage inverter (U2), which generates a mirrored negative rail from a single $2.7\,\mathrm{V} - 5.5\,\mathrm{V}$ supply at up to $200\,\mathrm{mA}$ and $2\,\mathrm{MHz}$ switching frequency. This eliminates the dual-rail bench supply typically required for op-amp circuits, significantly reducing setup complexity in classroom environments. All ten signal and power pins, including the inverting and non-inverting inputs, output, VCC, GND, VEE, and the U2 enable line (EN), are exposed through labeled $2.54\,\mathrm{mm}$ header connectors that map directly to the module pinout diagram. The module supports any standard single op-amp topology: inverting and non-inverting amplifiers, voltage followers, comparators, differentiators, and integrators — all configurable with external passive components from the PomeLabs Core Kit.

2. BOM Components

Ref.	Type	Value / Part	Role on This Module
U1	JFET-input op amp	TL081HIDR (TI)	Core signal amplification IC. Single-channel, $20\,\mathrm{V/\mu s}$ slew rate, $5.25\,\mathrm{MHz}$ GBW FET-input op amp in 8-pin SOIC. TL08xH grade: $-40\,\mathrm{{}^\circ C}$ to $+125\,\mathrm{{}^\circ C}$ , integrated EMI/RF filters.
U2	Switched-cap voltage inverter	LM2776DBVR (TI)	Charge-pump inverter converting positive VCC to mirrored negative rail ( $-V_{CC}$ ) at up to $200\,\mathrm{mA}$ . $2\,\mathrm{MHz}$ switching, $\geq 90\%$ efficiency. SOT-23-6 (DBV) package.
C1, C2	MLCC decoupling	$1\,\mathrm{\mu F}$ ceramic	Decoupling capacitors on U2 supply rails. X7R or X5R; voltage rating $\geq 10\,\mathrm{V}$ .
C3, C4	MLCC decoupling	$2.2\,\mathrm{\mu F}$ ceramic	Input (CIN) and flying (C1) capacitors for the LM2776DBVR charge pump. Low-ESR X7R or X5R preferred.
C5	MLCC decoupling	$1\,\mathrm{\mu F}$ ceramic	Output capacitor (COUT) for U2. Low-ESR ceramic minimizes ripple.
RH-5019	Test point / connector	Ref. designator	Negative rail ( $-V_{CC}$ ) measurement or inter-module chaining point at VOUT of U2.

Parameter	Symbol	Max Value	Unit
Supply voltage ( $V_S = V_+ - V_-$ )	$V_S$	$42\,\mathrm{V}$ ( $4.5\text{--}40\,\mathrm{V}$ operating)	V
Common-mode input voltage	$V_{CM}$	$(V_{CC^-}) - 0.5$ to $(V_{CC^+}) + 0.5$	V
Differential input voltage	$V_{ID}$	$V_S + 0.2$ (clamped)	V
Input signal current	$I_{IN}$	$\pm 10$	mA
Output short-circuit duration	$t_{SC}$	Continuous (1 ch at a time)	—
Operating junction temperature	$T_J$	$150$	°C
Storage temperature	$T_{STG}$	$-65$ to $+150$	°C

3.1.2 Recommended Operating Conditions

Parameter	Min	Typical	Max	Unit
Op-amp supply voltage range	$4.5$	$10$	$40$	V
Input signal frequency range	DC	—	$5.25\,\mathrm{MHz}$ GBW	—
Quiescent current (per channel)	—	$940$	—	µA
Gain-bandwidth product (GBW)	—	$5.25$	—	MHz
Slew rate	—	$20$	—	V/µs
Open-loop voltage gain ( $A_{OL}$ )	$118$	—	$125$	dB
Input offset voltage	—	$\pm 1$	$\pm 4$	mV
Input offset voltage drift	—	$\pm 2$	—	µV/°C
CMRR	$100$	—	$105$	dB
PSRR	—	$\pm 1$	$\pm 10$	µV/V
Input bias current	—	$\pm 1$	$\pm 120$	pA
Input voltage noise density ( $f = 1\,\mathrm{kHz}$ )	—	$37$	—	$\mathrm{nV/\sqrt{Hz}}$
THD	—	$0.003$	—	%
Operating temperature (ambient)	$-40$	$25$	$125$	°C

3.2 LM2776 (U2)

3.2.1 Absolute Maximum Ratings

Exceeding these values may permanently damage the module. Stress ratings only.

Parameter	Symbol	Max Value	Unit
Output current limit (short-circuit)	$I_{LIM}$	$400$	mA
UVLO threshold falling	$V_{UVLO-}$	$2.4$	V
Thermal shutdown junction temperature	$T_{SD}$	$150$	°C

3.2.2 Recommended Operating Conditions

Parameter	Min	Typical	Max	Unit
Input voltage ( $V_{IN}$ , VCC pin)	$2.7$	$5$	$5.5$	V
Internal positive rail (post-U2)	—	$+5$	—	V
Internal negative rail (post-U2)	—	$-V_{CC}$	—	V
Output current (continuous, to U1 supply)	$0$	—	$200$	mA
Quiescent supply current ( $I_Q$ , EN = 1, no load)	—	$100$	$200$	µA
Shutdown supply current ( $I_{SD}$ , EN = 0)	—	$0.1$	$1$	µA
Switching frequency ( $f_{SW}$ )	$1.7$	$2$	$2.3$	MHz
Output resistance ( $R_{OUT}$ )	—	$2.5$	—	Ω
EN threshold — enable (active-high)	$1.2$	—	—	V
EN threshold — shutdown	—	—	$0.4$	V
UVLO threshold rising	$2.6$	—	—	V
Package	—	SOT-23-6 (DBV), $2.90 \times 1.60\,\mathrm{mm}$	—	—

4. Pin Descriptions

The module exposes ten labeled pins. All signal pins are referenced to GND.

Pin Name	Channel	Direction	Description
S+_UL	Upper	Input	Non-inverting input ( $+$ ) of the upper op-amp channel. Connect signal to be amplified in-phase.
S+_UR	Upper	Output	Output of the upper op-amp channel. Drive loads $\geq 2\,\mathrm{k\Omega}$ . Do not short to GND.
S+_LL	Lower	Input	Non-inverting input ( $+$ ) of the lower op-amp channel.
S+_LR	Lower	Output	Output of the lower op-amp channel. Drive loads $\geq 2\,\mathrm{k\Omega}$ . Do not short to GND.
VCC	Both	Power In	Positive supply input to LM2776DBVR charge-pump inverter. Apply $2.7\,\mathrm{V} - 5.5\,\mathrm{V}$ DC.
VEE / −Vcc	Both	Power Out	Negative rail generated internally by U2 ( $\approx -V_{CC}$ ). Measurement only. Do not drive externally.
GND	Both	Ground	Common ground reference. Connect before any signal or power pins.
EN	Both	Input	Enable control for U2 (LM2776DBVR). Pull HIGH for normal operation; pull LOW for shutdown.

Correct power-up sequence:

Connect GND first to the common ground bus.
Connect VCC to a regulated DC source ( $2.7\,\mathrm{V} - 5.5\,\mathrm{V}$ ; $5\,\mathrm{V}$ recommended for classroom use).
Verify EN pin is HIGH (or tie to VCC) to enable U2.
Verify −Vcc pin reads approximately $-V_{CC}$ before connecting signal pins.
Connect signal inputs (S+_UL / S-_UL) only after power is stable.

Common wiring errors and consequences:

Mistake	Symptom	Correction
VCC out-of-range ( $> 5.5\,\mathrm{V}$ to U2)	U2 may enter thermal shutdown or be permanently damaged	Keep VCC $\leq 5.5\,\mathrm{V}$ for U2. If higher supply needed, add pre-regulator.
EN pin left floating	U2 may not start or behaves unpredictably	Tie EN HIGH (to VCC) for always-on mode, or control via GPIO. Pull to GND for shutdown.
Input floating (S+ or S−)	Output saturates to $\pm V_{CC}$ or oscillates	Connect both inputs. Use resistor to GND on unused inputs.
Driving −Vcc / VEE from external source	U2 permanently damaged; may damage U1	VEE / −Vcc is an output only. Never apply external voltage to this pin.
Load resistance $< 1\,\mathrm{k\Omega}$ on OUT pin	Reduced output swing, distortion	Drive loads $\geq 2\,\mathrm{k\Omega}$ .
Input signal beyond $\pm V_{CC}$ range	Clipped output; possible latch-up	Keep signal inputs within $(V_{CC^-} + 1.5\,\mathrm{V})$ to $(V_{CC^+})$ . Add input protection resistor.
C3/C4/C5 wrong type (Y5V/Z5U ceramic)	U2 output ripple high, efficiency reduced	Use X7R or X5R MLCCs. Y5V/Z5U lose $> 80\%$ capacitance under DC bias.